1. Field of the Invention
The present invention relates to a circuit for detecting the coincidence between a binary information unit stored therein and an external datum.
2. Description of the Related Art
In semiconductor memories it is often necessary to provide programmable circuits for storing a binary information unit and for performing a comparison between the datum stored therein and a datum carried by a generic control line, in order to detect the coincidence between the two data.
For example, a known application of such circuits is in the implementation of redundancy memory. Conventionally, in semiconductor memories it is a common technique to provide, within the memory device chip, redundancy memory elements suitable to functionally replace defective memory elements.
The redundancy memory elements are generally formed by bit lines and/or word lines of redundancy memory cells. During the in-factory testing of the memory device, the redundancy bit lines and word lines are associated with respective defective bit lines and word lines, respectively. In this way, during normal operation, redundancy bit lines and word lines are activated whenever the associated defective bit lines and word lines are addressed, and the latter are not accessed.
To perform this function, programmable non-volatile memory registers (redundancy registers) must be provided in the memory device to permanently store the addresses of the defective bit lines and word lines for each redundancy bit line, as well as for each redundancy word line, a respective non-volatile memory register must be provided to store the address of the defective bit line or word line which is to be replaced by the redundancy bit line or word line.
The redundancy registers are formed by a number of programmable non-volatile memory units at least equal to the number of column address bits or row address bits. Each programmable non-volatile memory unit must store a respective address bit of the address configuration of a defective bit line or word line, and must perform a comparison of the address bit stored therein with the corresponding bit of the current address supplied to the memory device. When the current address bit coincides with the address bit stored in the memory unit, a coincidence signal is activated. If all the current address bits coincide with the defective address bits stored in the memory units of a redundancy register, the associated redundancy bit line or word line is activated in substitution for the defective bit line or word line.
The programmable elementary memory units should occupy a small area and have low power consumption, because they are often provided in great number. Also, they should be fast in performing the comparison between the datum stored therein with the datum carried by the associated control line. For example, considering the application described above, the detection of the coincidence of the current address with a defective address stored in a redundancy register must be performed as fast as possible so as not to degrade the access time of the memory device.
FIG. 1 schematically shows the structure of a known programmable elementary memory unit. Block 1 schematizes a programmable memory element (generally a non-volatile memory element such as, for example, an EPROM cell) and the associated sensing circuit for sensing the datum stored in the programmable memory element; an output line 2 of block 1 carries a logic level representative of the datum stored in the programmable memory element. A buffer stage comprising a cascade of two inverters I1, I2 is provided. Inverters I1, I2 control a digital comparator comprising two transfer gates T1, T2. Transfer gate T1 has an N-channel MOSFET controlled by an output 4 of I2 and a P-channel MOSFET controlled by an output 3 of inverter I1. Transfer gate T2 has an N-channel MOSFET controlled by the output 3 of inverter I1 and a P-channel MOSFET controlled by the output 4 of inverter I2. According to the logic level of line 2, either transfer gate T1 is open and transfer gate T2 closed or transfer gate T1 is closed and transfer gate T2 open. Transfer gate T1 receives at its input, a control line Ax, for example an address line, while transfer gate T2 receives at its input a control line An which carries the logic complement of the datum carried by line Ax. When the signal line An is not available, it can be locally generated by means of an inverter I3 (shown in dashed line). The outputs of transfer gates T1 and T2 are commonly connected to an output line O.
Supposing that line 2 carries a "1", transfer gate T1 is open and transfer gate T2 is closed, and output line O=Ax; if line Ax="1" then output line O="1", while if line Ax="0" then output line O=0. If instead line 2 carries a "0", transfer gate T1 is closed and transfer gate T2 is open, and output line O=An; if line Ax="1" then line An="0" and output line O="0", while if line Ax=0 then An="1" and ="1". In other words, if the datum stored in the programmable memory element is a logic "1", then output line O is a "1" only if line Ax is a "1"; if instead the datum stored in the programmable memory element is a logic "0", then output line O is a "1" only if line Ax is a "0". Differently said, output line O is equal to "1" only if the datum carried by line Ax coincides with the datum stored in the programmable memory element.
Up to now, the skilled persons have considered the provision of the buffer stage formed by inverters I1 and I2 essential to prevent malfunctioning of the sensing circuit associated with the programmable memory element, such as erroneous sensing of the actual programming state of the memory element determined by the loading of the sensing circuit by the circuits downstream of it. Inverters I1 and I2, decoupling the sensing circuit from the remaining circuits, assure that such errors are prevented. However, invertors I1 and I2 occupy a finite chip area, slow the comparison process and introduce extra power consumption. These problems are exacerbated by the fact that generally a great number of the circuits shown in FIG. 1 need to be integrated in a memory device chip.